In DC-DC power supplies, optimization of the control MOSFET (metal oxide semiconductor field effect transistor) requires minimization of both conduction and switching losses. Historically, planar or trench DMOS (diffused MOS) devices have been used for switching due to their lower resistance and thus low conduction loss. Those MOSFET structures have utilized drain contact through the substrate of the wafer. Although those structures provide low resistance, they are not satisfactory with regard to low switching loss. LDMOS (laterally diffused MOS) devices have historically been used in RF (radio frequency) applications that require very low switching loss at high frequency. If LDMOS devices can achieve resistance comparable to that of planar or trench DMOS devices, they will have higher conversion efficiency due to their reduced switching loss.
Techniques for reducing the LDMOS cell pitch are needed to obtain lower resistance. In the co-packaging of both control and synchronous MOSFETs in a single package, it is desirable to have the control MOSFET with a drain contact at the top of the die and the source contact at the bottom of the die. To reduce the package footprint, the control MOSFET can be stacked on top of the synchronous MOSFET.
In a conventional RF LDMOS power transistor, in order to have the drain contact of the LDMOS at the top of the die, the source contact must be at the bottom of the die. This requires a contact between the n+ surface source region and the p+ substrate. It is important that this contact consume a small area because this will reduce the cell pitch and thus reduce the total resistance of the MOSFET for a given area. It is also important that the contact have very low resistance so that it does not significantly contribute to the resistance of the MOSFET. In addition, a gate shield connected to the source electrode should be included to reduce the electric field between the gate and drain regions of the device. The gate shield resistance should be low for good high frequency performance; this can be achieved if the gate shield is connected locally to the source. In a discrete power MOSFET, the gate shield cannot be made from metal because there can be only one layer of metal in the process and that layer of metal is used for the drain connection and gate routing. Thus, the gate shield is made of a conductor lying below the metal. The conductor used for such a shield is heavily doped polysilicon due to its ease of formation and its stability.
Previous attempts at forming a source-to-substrate connection have used a budding contact from the n+ source to a p+ sinker. This technique consumes too much area and, because it does not use metallization to contact the substrate, has high resistance. Another technique etches a trench down to the substrate and connects the source to the substrate using silicide and aluminum metal. This technique also consumes too much area because the trench must have a very sloped profile to avoid aluminum voiding. In forming a contact, a trench can be etched and metallization used to connect the n+ source to the p+ substrate because this reduces the resistance. However, the metallization must be able to reach the p+ substrate through a narrow opening.